This invention relates generally to a method of forming a high performance printed wiring circuit board structure having high circuit density per unit area and, more particularly, to a method of forming such a high performance printed wiring circuit board structure having plated through holes which are unfilled and extend from one surface of the board to the other.
With the recent trend toward reduced sizes in electronic components and the resulting high density requirements for electronic packaging, such as printed wiring board structures, there have been increased demands to design a process that will generate high quality, high density printed wiring boards efficiently, wherein there are unfilled plated through holes.
The need for high density electronic devices, such as very large scale integrated circuits (VLSIs) has greatly increased. The space or area available outside of the VLSI in which to make the large number of necessary connections to and from it and to provide the necessary circuitry is becoming very small as measured by previous standards. Contrary to the density increase in the VLSIs, the density of the passive circuits on printed wiring boards has increased (i.e., the parts have decreased in size) by only a relatively small factor (i.e., less than about 4 to 1). This presents the difficulty of providing circuitry on the printed wiring board to the VLSIs which is small enough to fit the spaces available and which is also sufficiently reliable and readily manufacturable to be economically useful.
One of the most significant limitations on creating high density fine line circuitry on printed wiring boards is the generally known problem of trying to obtain anisotropic etching. It is known that etching metals, especially copper metal, is not an anisotropic process. That is, vertical etching is not feasible without some amount of unwanted horizontal etching. This creates a situation in which the features and circuitry so formed can be severely undercut, leading to different types of failures and reject material. In other words, this presents a limitation on the type of electrical circuitry that can be formed by the subtractive etching process. The problem is exacerbated by having thick metal layers. However, this is precisely the situation that is created when standard vias or through holes are part of the manufacturing process.
It is well known that the plating within a through hole is thinner than the plating on the external surface; yet a minimum thickness in the through hole is required in order to provide an adequate and reliable electrical connection between the circuitry on the opposing faces or at various levels within the printed wiring board. Therefore, the general practice is to plate excess material on the lateral faces in order to insure sufficient plating of the through holes. The effect of this is that a greater than necessary thickness of the lateral surface plating then causes greater amounts of undercutting during the circuitization process by etching. To compensate for this effect, the circuitry lines are designed wider and farther apart than otherwise required or desired. To resolve this problem, thinning down of the lateral faces by etching, prior to circuitization, has been suggested. If chemically performed, this process also undesirably etches within the plated through holes which negates obtaining the required thickness of the plated through holes. Mechanical etching of the lateral surfaces is possible but general practice for a process of this type is extremely slow.
The area of printed wiring board manufacturing most affected by these advances in technology are the relatively thick processor or backpanel type boards. These boards vary in thickness based upon the application from about 40 mils to greater than 400 mils. Because of the thickness of these boards and the aforementioned difficulties with plating and etching, final assembly of the finished functional product often includes compliant pin connectors for card insertion, harcon pin insertions for MCM modules or surface mount components. Current advances in technology are permitting the direct attachment of chips (DCA) to large panels, as well as solder ball arrays (land grid areas or ball grid arrays as an example), for direct attachment of MCM""s.
The deficiencies in the current art limit the circuitization of features needed to direct attachment of assemblies components other than surface mount discrete components. A standard print and etch method of fabrication is limited by the aforementioned thickness of surface copper being etched to produce the features. Pattern plating operations, either electroplating or full build, are limited by the photoresist resolution in the fine areas. This is because one mil of plating is still required in the plated through holes, resulting in the use of a minimum one mil thick pattern plating photoresist. As photoresist thicknesses increase, the ability to resolve finer lines and spaces is limited.
Also, another deficiency of the current art is the ability of the thin photoresists to tent plated through holes (PTH) to protect them from etching during the circuitization process. Printed wiring boards needing pinned components require relatively larger diameter holes (30 mils and up) than thinner boards where small vias are used for wiring through the board. This invention aids the circuitization by providing a temporary support for the photoresist over the relatively large holes.
Hayakawa et al, in U.S. Pat. No. 4,383,363, teach the use of conductive materials for filling through holes, but no mention is made of non-conductive materials for this application. Hayakawa et al do not disclose the significance of a thin metallic layer for creating high density circuitry. The purpose of the conductive filling in their invention is solely to electrically connect the two major faces of the substrate, not to protect the metal layer in the through hole, as in the present invention.
Kawakami et al, in U.S. Pat. No. 5,220,135, disclose a conductive filling within the through hole of an insulative substrate. As in U.S. Pat. No. 4,383,363, supra, no mention is made of protecting the metal layer within the plated through hole.
Bhatt et al, in U.S. Pat. Nos. 5,557,844 and 5,487,218, disclose a process and a material for forming filled through holes and blind holes. The filler material is an organic polymeric material optionally with particulate filler. The filler composition is compounded to have a coefficient of thermal expansion matching the coefficient of thermal expansion of the dielectric substrate. The fill material may be either conductive or non-conductive. These patents teach first laminating a copper foil to a dielectric substrate followed by thinning the foil to an acceptable thickness, then drilling through holes and subsequently electroless plating into the through holes to create a conductive layer therein. The filling in the ""844 patent occurs after the etching process of the lateral metal layers, unless the present invention which requires that the filler be present during the etching process. Furthermore, the specific benefit of the present invention is that both the lateral metallic layers and the through hole metal layer are applied simultaneously, unlike the ""844 disclosure, which specifies that these steps occur sequentially.
One attempt to solve this problem is shown and described in U.S. patent application Ser. No. 09/345,573, filed Jun. 30, 1999, entitled xe2x80x9cFine Pitch Circuitization with Filled Plated Through Holesxe2x80x9d (Attorney Docket EN9-98-113). This solution is effective for many different applications. However, it does have limitations for certain applications. Specifically, when the circuitized structure is used for a pin in hole connection, the fillings in the hole prevent the pins from entering the holes and making the required connections. Thus, for pin in hole connection, through holes need to be free of filling material to allow the pins to enter the openings. Moreover, in some instances, the filler material used may tend to interfere with the various subsequent processing steps of the circuitized substrate.
Therefore, it is a principal object of the present invention to provide an improved process of forming a circuitized substructure, resulting in plated through holes free of filler material in the final product.
According to the present invention, there is provided a method of making a circuitized substrate having plated through holes free of filler material. The method comprises the steps of providing a dielectric substrate having first and second opposite faces. At least one via hole is formed, extending from one face to the other. A first electrically conductive layer is applied onto the top and bottom faces of the dielectric member and onto the side wall of the via. First layers of photoresist are applied to each layer of conductive material and forced at least partially into the via hole. Thereafter, the first layers of photoresist are selectively exposed and developed to remove all of the photoresist, except that photoresist which is disposed in the via holes. Thereafter, a portion of the faces of the metal coatings on the surfaces of dielectric material and any photoresist remaining in the holes which extends above the layers of electrically conductive material are removed to form a planar surface of a thickness thinner than the thickness of the metal in the through hole. Thereafter, a second layer of photoresist material is applied to both the surfaces of the metal on both faces of the dielectric material and exposed to a desired circuit pattern. Thereafter, the second layers of the photoresist material are developed to reveal the underlying metal which is then etched to form a circuit pattern of said metal layer on both faces. Thereafter, the second layers of the remaining photoresist are stripped and also the photoresist remaining in the holes is stripped, thereby to provide a circuitized substrate with plated through holes having openings extending from the upper face of the substrate to the lower face of the substrate.